Nonvolatile memory such as a programmable read-only memory (PROM) is used to store data for extended periods of time. PROMs are faster than other forms of nonvolatile storage, such as magnetic or optical tapes or discs, and are much like volatile storage such as random access memory (RAM). PROMs have an advantage over RAM in that the stored data is not lost when power is disconnected. PROMs come in many different varieties, such as those that are eraseable and rewriteable.
A system including a volatile programmable logic device (PLD), such as an FPGA, typically includes a nonvolatile memory for storing configuration data for the PLD. When the system is powered up, a data stream with the configuration information in the nonvolatile memory is loaded into the volatile PLD to configure it so the system can become operational. PLDs have the advantage that they can be reconfigured while in the system, thus allowing the system to take on a different function without having to change any of the hardware in the system. It is also possible to change the hardware in the system to add new features, increase speed, or otherwise upgrade the system, and this typically requires reconfiguring the PLD to implement the new features or to work with other new hardware.
In certain cases, it is advantageous to have the ability to store multiple data streams in the nonvolatile memory so that the configuration of the PLD can be changed by selecting a different data stream without having to power down the system, and without having to reprogram or replace the PROM. For example, while a system is being developed, it may also be desirable to be able to change configurations and test multiple data streams. For another example, it may be desirable to allow for different data streams to be available so that a PLD can be customized for a particular application or so that one PLD may perform different operations at different times. As a further example, multiple data streams may also be needed in a system with multiple PLDs performing various functions, where each PLD has different programming data.
In some prior art implementations, an external controller is required to allow multiple data streams to be stored in one memory device. The external controller would locate the selected data stream in the memory device via select lines that map to memory addresses. This technique has the disadvantage that the number of data stream select pins limits the number of possible data streams that can be stored in the memory device. The maximum number of selectable data streams could be reached before the memory device was full, meaning that part of the storage space of the memory device would be wasted. This technique also requires significant external logic and external resources. One example of this prior art implementation is the Xilinx® System ACE™ MPM Solution, as described in Advanced Product Specification DS087 (v1.2) dated Jun. 7, 2002, available from Xilinx, Inc.
Another prior art technique for storing and retrieving multiple data streams includes using multiple memory devices. In one implementation, each memory device can store a different data stream, and an external muxing circuit is required to select the desired memory device and data stream. The size of the muxing circuit needed depends on the number of memory devices (and data streams) that are used. This technique also requires that a separate enable signal from the muxing circuit be routed to each memory device, increasing the demand on limited board-level or system-level routing resources.
In another prior art technique, shown in FIG. 1, multiple memory devices 121 are chained together, sharing certain input signals, including select lines. Each select line combination is associated with one logical block in each memory device (e.g., combination 00 is associated with logical block 0, combination 01 with logical block 1, etc.) When such a memory device is enabled, it will output the data contained in the logical block that is associated with the particular select line combination being asserted. One particular select line combination is assigned to each data stream stored in the multiple memory devices. In the example shown in FIG. 1, there are four data streams (labeled A–D) stored in the four memory devices shown. Select line combination 00 in this example has been assigned to data stream A, 01 to B, 10 to C, and 11 to D. Thus, data stream A is stored in logical block 0 in each memory device (since the select line combination assigned to data stream A corresponds to logical block 0), data stream B in logical block 1, etc. One disadvantage of this prior art technique is that a great deal of space in the memory devices is wasted. For example, two blocks in memory device PROM_2 and three blocks in PROM_3 are not used, and are wasted extra storage space since the four data streams A–D have varying lengths and therefore each occupy a different number of blocks. More specifically, in the example shown in FIG. 1, since data stream A is four blocks long, it requires a minimum of four memory devices; however, data stream B is only two blocks long, it requires only two memory devices, and logical block 1 (assigned to data stream B) in two of the four memory devices is not used and is wasted. A system may require different length data streams for programming multiple devices of different sizes. Examples of prior art devices making use of this technique are the Atmel® AT17F series of In-System Programmable Configuration PROMs available from Atmel Corporation.
Therefore, it would be desirable for a memory device, or a group of memory devices, to allow for better utilization of the available storage space, and to allow for storage of many data streams with a minimal amount of external logic and/or routing.